The present invention relates to a timing-phase recovery circuit, and more particularly a timing-phase recovery circuit located in a receiver station of a carrier-modulated data communication system.
In a carrier-modulated data communication system, a carrier-modulated analogue signal is transmitted from a sender station to a receiver station, and a carrier-modulated analogue signal is produced, in the sender station, based on a PSK (Phase Shift Keying) modulation mode, a QAM (Quadrature Amplitude Modulation) mode or an AM (Amplitude Modulation) mode. In order to establish any of the above mentioned modulation modes, the analogue signal to be transmitted from the sender station is modulated by data to be communicated, in synchronism with a predetermined timing signal having a constant frequency. In the receiver station, which receives the analogue signal, the received input analogue signal is demodulated and the original data is reproduced by means of a timing recovery circuit in synchronous with a timing signal. This timing signal should be identical with the aforesaid timing signal generated in the sender station. Accordingly, the timing signal of the receiver station is tuned to a timing signal which is extracted from the input analogue signal. A tuning operation between the extracted timing signal and the timing signal generated in the receiver station must be promptly completed. This is because an automatic equalizer, an automatic gain control circuit and so on of the receiver station can start respective operations after the timing signal of the receiver station has correctly been tuned to the extracted timing signal. Further, according to world standards pertaining to the carrier-modulation data communication system, the receiver station must be set in normal operating condition in a very short period, such as 50 ms, from the time when the input analogue signal is applied thereto. Thus, the timing-phase recovery circuit of the receiver station must complete the tuning operation in a very short time.
In the prior art, the timing-phase recovery circuit consists of an analogue circuit. The timing-phase recovery analogue circuit is described, for example in IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-22, No. 7, July 1974, on pages 913 through 919, entitled "Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme" and in IEEE TRANSACTIONS ON COMMUNICATIONS, November 1975, on pages 1327 through 1331, entitled "Envelope-Derived Timing Recovery in QAM and SQAM Systems". Since the timing-phase recovery analogue circuit deals with an analogue timing signal, the so-called zero crossing can be detected in a very short time. The zero crossing is very useful for tuning the timing signal of the receiver station to the extracted timing signal contained in the input analogue signal.
In recent years, a demand has arisen for constructing the timing-phase recovery circuit as a digital circuit. A timing-phase recovery digital circuit may easily be fabricated as an LSI (Large Scale Integration) circuit, and accordingly the timing-phase recovery digital circuit becomes cheaper in cost, more accurate in operation and smaller in size, when compared to prior timing-phase recovery analogue circuits. In general, it is easy for a person skilled in the art to create the timing-phase recovery digital circuit according to the corresponding timing-phase recovery analogue circuit, merely by substituting the analogue circuit elements of the analogue circuit for the corresponding digital circuit elements. However, the above-mentioned timing-phase recovery digital circuit creates a serious defect in the aforesaid tuning operation. That is, the digital circuit cannot complete the tuning operation in a very short time. The reason why the tuning operation can not be completed in a very short time, will be clarified hereinafter. However, in short, the reason resides in the fact that, in the timing-phase recovery digital circuit, the aforesaid zero crossing cannot be detected from the input analogue signal in a very short period of time.